Organic integrated circuits are known.
Applicant's earlier patents directed to semiconductor device manufacturing processes include:
U.S. Pat. No. 6,013,534 to Mountain, entitled “Method of Thinning Integrated Circuits Received in Die Form”, issued Jan. 11, 2000, which is incorporated herein by reference; and U.S. Pat. No. 6,017,822 to Mountain, entitled “Method of Thinning Semiconducted Wafer of Smaller Diameter than Thinning Equipment Was Designed For”, issued Jan. 25, 2000, and which is incorporated herein by reference.
Additional known United States patent documents include:
U.S. Pat. No. 5,970,318 to Choi et al.;
U.S. Pat. No. 6,403,397 B1 to Katz;
U.S. Pat. No. 6,551,717 B2 to Katz et al.;
U.S. Pat. No. 6,150,668 to Bao et al.;
U.S. Pat. No. 6,635,508 B2 to Arai et al.;
U.S. Pat. No. 6,303,219 B1 to Sawamura et al.; and
U.S. Pat. Pub. No. US2002/0072149 A1 to Yoshida.
Transistors and interconnect patterning processes are known in the wafer fabrication and wafer-level packaging industries. Known organic flexible substrates which have been proposed for organic integrated circuits typically have relatively low service temperatures; i.e. service temperatures of 150° C. or less.
There is a need for flexible integrated circuits having longer service lives, greater service temperature ranges, and more varied and larger configurations than known in the art.